Write combining

Write combining cannot be used for general memory access (data or code regions) due to the weak ordering. Write-combining does not guarantee that the combination of writes and reads is done in the expected order. For example, a write/read/write combination to a specific address would lead to the write combining order of read/write/write which can lead to obtaining wrong values with the first read (which potentially relies on the write before).

In order to avoid the problem of read/write order described above, the write buffer can be treated as a fully associative cache and added into the memory hierarchy of the device in which it is implemented.^[2] Adding complexity slows down the memory hierarchy so this technique is often only used for memory which does not need strong ordering (always correct) like the frame buffers of video cards.

• Framebuffer (FB), and when linear: LFB
• Memory type range registers (MTRR) – the older x86 cache control mechanism
• Page attribute table (PAT) – x86 page table extension that allows fine-grained cache control, including write combining
• Page table
• Uncacheable speculative write combining (USWC)
• Video Graphics Array (VGA), and Banked (BVGA) Frame Buffer

1. ^ Intel (November 1998). "Write Combining Memory Implementation Guidelines" (PDF). Intel. Retrieved 2010-11-02.
2. ^ BearWindows (2008-09-01). "Video Hardware Acceleration in DOS Environment". BearWindows Vault. Archived from the original on July 24, 2008. Retrieved 2010-11-02.

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